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13. 
Cover image for Transactions on High-Performance Embedded Architectures and Compilers II
Transactions on High-Performance Embedded Architectures and Compilers II
by 
Stenström, Per. editor. (orcid)0000-0002-7441-8245
https://doi.org/10.1007/978-3-642-00904-4
Format: 
Excerpt: 
Computer arithmetic and logic units.
14. 
Cover image for High Performance Embedded Architectures and Compilers Fourth International Conference, HiPEAC 2009
High Performance Embedded Architectures and Compilers Fourth International Conference, HiPEAC 2009
by 
Seznec, André. editor.
https://doi.org/10.1007/978-3-540-92990-1
Format: 
Excerpt: 
Computer arithmetic and logic units.
15. 
Cover image for Computer Performance Evaluation and Benchmarking SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009, Proceedings
Computer Performance Evaluation and Benchmarking SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009, Proceedings
by 
Kaeli, David. editor.
https://doi.org/10.1007/978-3-540-93799-9
Format: 
Excerpt: 
Logic design.
16. 
Cover image for Job Scheduling Strategies for Parallel Processing 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009, Revised Papers
Job Scheduling Strategies for Parallel Processing 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009, Revised Papers
by 
Frachtenberg, Eitan. editor.
https://doi.org/10.1007/978-3-642-04633-9
Format: 
Excerpt: 
Logic design.
17. 
Cover image for A Practical Introduction to Computer Architecture
A Practical Introduction to Computer Architecture
by 
Page, Daniel. author.
https://doi.org/10.1007/978-1-84882-256-6
Format: 
Excerpt: 
Computer arithmetic and logic units.
18. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Revised Selected Papers
by 
Svensson, Lars. editor.
https://doi.org/10.1007/978-3-540-95948-9
Format: 
Excerpt: 
Computer arithmetic and logic units.
19. 
Cover image for High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings
High Performance Embedded Architectures and Compilers Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings
by 
Stenström, Per. editor. (orcid)0000-0002-7441-8245
https://doi.org/10.1007/978-3-540-77560-7
Format: 
Excerpt: 
Computer arithmetic and logic units.
20. 
Cover image for Job Scheduling Strategies for Parallel Processing 13th International Workshop, JSSPP 2007, Seattle, WA, USA, June 17, 2007, Revised Papers
Job Scheduling Strategies for Parallel Processing 13th International Workshop, JSSPP 2007, Seattle, WA, USA, June 17, 2007, Revised Papers
by 
Frachtenberg, Eitan. editor.
https://doi.org/10.1007/978-3-540-78699-3
Format: 
Excerpt: 
Logic design.
21. 
Cover image for Hybrid Systems: Computation and Control 11th International Workshop, HSCC 2008, St. Louis, MO, USA, April 22-24, 2008, Proceedings
Hybrid Systems: Computation and Control 11th International Workshop, HSCC 2008, St. Louis, MO, USA, April 22-24, 2008, Proceedings
by 
Egerstedt, Magnus. editor.
https://doi.org/10.1007/978-3-540-78929-1
Format: 
Excerpt: 
Computer Science Logic and Foundations of Programming.
22. 
Cover image for High-Level Synthesis from Algorithm to Digital Circuit
High-Level Synthesis from Algorithm to Digital Circuit
by 
Coussy, Philippe. editor.
https://doi.org/10.1007/978-1-4020-8588-8
Format: 
Excerpt: 
Logic design.
23. 
Cover image for Transactions on High-Performance Embedded Architectures and Compilers I
Transactions on High-Performance Embedded Architectures and Compilers I
by 
O'Boyle, Mike. editor.
https://doi.org/10.1007/978-3-540-71528-3
Format: 
Excerpt: 
Computer arithmetic and logic units.
24. 
Cover image for Job Scheduling Strategies for Parallel Processing 12th International Workshop, JSSPP 2006, Saint-Malo, France, June 26, 2006, Revised Selected Papers
Job Scheduling Strategies for Parallel Processing 12th International Workshop, JSSPP 2006, Saint-Malo, France, June 26, 2006, Revised Selected Papers
by 
Frachtenberg, Eitan. editor.
https://doi.org/10.1007/978-3-540-71035-6
Format: 
Excerpt: 
Logic design.
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