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1. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings
by 
Azemard, Nadine. editor.
https://doi.org/10.1007/978-3-540-74442-9
Format: 
Excerpt: 
Computer arithmetic and logic units.
2. 
Cover image for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings
by 
Vounckx, Johan. editor.
https://doi.org/10.1007/11847083
Format: 
Excerpt: 
Computer arithmetic and logic units.