Search Results for Logic. - Narrowed by: Electrical engineering. SirsiDynix Enterprise http://librarycatalog.yyu.edu.tr/client/en_US/default/default/qu$003dLogic.$0026qf$003dSUBJECT$002509Subject$002509Electrical$002bengineering.$002509Electrical$002bengineering.$0026ps$003d300$0026isd$003dtrue?dt=list 2025-02-13T15:15:22Z Fuzzy Logic, Identification and Predictive Control ent://SD_ILS/0/SD_ILS:149412 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Espinosa Oviedo, Jairo Jose. author.<br/><a href="https://doi.org/10.1007/b138626">https://doi.org/10.1007/b138626</a><br/>Format:&#160;Electronic Resources<br/> Logic Synthesis for Compositional Microprogram Control Units ent://SD_ILS/0/SD_ILS:157885 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Barkalov, Alexander. author.<br/><a href="https://doi.org/10.1007/978-3-540-69285-0">https://doi.org/10.1007/978-3-540-69285-0</a><br/>Format:&#160;Electronic Resources<br/> Computation Engineering Applied Automata Theory and Logic ent://SD_ILS/0/SD_ILS:152760 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Gopalakrishnan, Ganesh. author.<br/><a href="https://doi.org/10.1007/0-387-32520-4">https://doi.org/10.1007/0-387-32520-4</a><br/>Format:&#160;Electronic Resources<br/> Asynchronous Operators of Sequential Logic: Venjunction &amp; Sequention Digital Circuit Analysis and Design ent://SD_ILS/0/SD_ILS:144317 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Vasyukevich, Vadim. author.<br/><a href="https://doi.org/10.1007/978-3-642-21611-4">https://doi.org/10.1007/978-3-642-21611-4</a><br/>Format:&#160;Electronic Resources<br/> Fundamentals of Switching Theory and Logic Design A Hands on Approach ent://SD_ILS/0/SD_ILS:152653 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Astola, Jaakko. author.<br/><a href="https://doi.org/10.1007/0-387-30311-1">https://doi.org/10.1007/0-387-30311-1</a><br/>Format:&#160;Electronic Resources<br/> Model and Design of Bipolar and MOS Current-Mode Logic CML, ECL and SCL Digital Circuits ent://SD_ILS/0/SD_ILS:143461 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Alioto, Massimo. author.<br/><a href="https://doi.org/10.1007/1-4020-2888-1">https://doi.org/10.1007/1-4020-2888-1</a><br/>Format:&#160;Electronic Resources<br/> The Unknown Component Problem Theory and Applications ent://SD_ILS/0/SD_ILS:153344 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Villa, Tiziano. author.<br/><a href="https://doi.org/10.1007/978-0-387-68759-9">https://doi.org/10.1007/978-0-387-68759-9</a><br/>Format:&#160;Electronic Resources<br/> Electrical engineering 101 : everything you should have learned in school-- but probably didn't ent://SD_ILS/0/SD_ILS:198642 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Ashby, Darren.<br/>ScienceDirect <a href="http://www.sciencedirect.com/science/book/9780123860019">http://www.sciencedirect.com/science/book/9780123860019</a><br/>Format:&#160;Electronic Resources<br/> Fault-Tolerance Techniques for SRAM-Based FPGAs ent://SD_ILS/0/SD_ILS:152704 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Kastensmidt, Fernanda Lima. author.<br/><a href="https://doi.org/10.1007/978-0-387-31069-5">https://doi.org/10.1007/978-0-387-31069-5</a><br/>Format:&#160;Electronic Resources<br/> A Roadmap for Formal Property Verification ent://SD_ILS/0/SD_ILS:137372 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Dasgupta, Pallab. author.<br/><a href="https://doi.org/10.1007/978-1-4020-4758-9">https://doi.org/10.1007/978-1-4020-4758-9</a><br/>Format:&#160;Electronic Resources<br/> Layoutsynthese elektronischer Schaltungen - Grundlegende Algorithmen f&uuml;r die Entwurfsautomatisierung ent://SD_ILS/0/SD_ILS:187678 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Lienig, Jens. author.<br/><a href="https://doi.org/10.1007/3-540-29942-4">https://doi.org/10.1007/3-540-29942-4</a><br/>Format:&#160;Electronic Resources<br/> Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings ent://SD_ILS/0/SD_ILS:143157 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Paliouras, Vassilis. editor.<br/><a href="https://doi.org/10.1007/11556930">https://doi.org/10.1007/11556930</a><br/>Format:&#160;Electronic Resources<br/> New Algorithms, Architectures and Applications for Reconfigurable Computing ent://SD_ILS/0/SD_ILS:137003 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Lysaght, Patrick. editor.<br/><a href="https://doi.org/10.1007/1-4020-3128-9">https://doi.org/10.1007/1-4020-3128-9</a><br/>Format:&#160;Electronic Resources<br/> Taxonomies for the Development and Verification of Digital Systems ent://SD_ILS/0/SD_ILS:136113 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;Bailey, Brian. editor.<br/><a href="https://doi.org/10.1007/b104217">https://doi.org/10.1007/b104217</a><br/>Format:&#160;Electronic Resources<br/> Mikrorechner-Technik &Uuml;bungen und L&ouml;sungen ent://SD_ILS/0/SD_ILS:191198 2025-02-13T15:15:22Z 2025-02-13T15:15:22Z by&#160;B&auml;hring, Helmut. author.<br/><a href="https://doi.org/10.1007/b138234">https://doi.org/10.1007/b138234</a><br/>Format:&#160;Electronic Resources<br/>